Altera cyclone V Technical Reference page 1146

Hard processor system
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cv_5v4
2016.10.28
Bit
1
cmdexecstat
0
execcmd
flashcmdaddr
Module Instance
qspiregs
Offset:
0x94
Access:
RW
31
30
15
14
flashcmdaddr Fields
Bit
31:0
addr
Quad SPI Flash Controller
Send Feedback
Name
Command execution in progress.
Value
0x1
0x0
Execute the command.
Value
0x1
0x0
0xFF705000
29
28
27
26
13
12
11
10
Name
This should be setup before triggering the command
with execute field (bit 0) of the Flash Command
Control register. It is the address used by the
command specified in the opcode field (bits 31:24) of
the Flash Command Control register.
Description
Description
Command Execution Status
No Action
Description
Execute Command
No Action
Base Address
Bit Fields
25
24
23
22
addr
RW 0x0
9
8
7
6
addr
RW 0x0
Description
flashcmdaddr
Access
Register Address
0xFF705094
21
20
19
18
5
4
3
2
Access
15-57
Reset
RO
0x0
RW
0x0
17
16
1
0
Reset
RW
0x0
Altera Corporation

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