Altera cyclone V Technical Reference page 1168

cv_5v4
2016.10.28
To transfer the 64 words, the program instructs the DMAC to perform 16 AXI transfers. Each AXI
transfer consists of a 4-beat burst (SB=4, DB=4), each beat of which moves a word of data (SS=32, DS=32).
The following program shows the use of the:
•
DMAWFP periph
•
DMASTPB and DMASTPS
Example 16-1: Peripheral Length Management Program
# Set up for burst transfers (4-beat burst, so SB4 and DB4), (word data
width, so SS32 and DS32)
DMAMOV CCR SB4 SS32 DB4 DS32
DMAMOV SAR ...
DMAMOV DAR ...
# Initialize peripheral '0'
DMAFLUSHP P0
# Perform peripheral transfers
# Outer loop - DMAC responds to peripheral requests until peripheral sets
drlast_0 = 1
DMALPFE
# Wait for request, DMAC sets request_type0 flag depending on the request
type it receives
DMAWFP 0, periph
# Set up loop for burst request: first 15 of 16 sets of transactions
# Note: B suffix - conditionally executed only if request_type0 flag = Burst
DMALP 15
DMALDB
DMASTB
# Only loop back if servicing a burst, otherwise treat as a NOP
DMALPENDB
# Perform final transaction (16 of 16). Send the peripheral acknowledgement
of burst request completion
DMALDB
DMASTPB P0
# Perform transaction if the peripheral signals a single request
# Note: S suffix - conditionally executed only if request_type0 flag = Single
DMALDS
DMASTPS P0
# Exit loop if DMAC receives the last request, that is, drlast_0 = 1
DMALPEND
DMAEND
DMAC Length Management
The DMAC controls the total amount of data. The peripheral uses the peripheral request interface to notify
the DMAC when it requires the DMAC to transfer data to or from the peripheral. The DMA channel
thread controls how the DMAC responds to the peripheral requests.
The following constraints apply to DMAC length management:
• The total quantity of data for all the single requests from a peripheral must be less than the quantity of
data for a burst request for that peripheral.
Note: The
Altera recommends that you do not update a
channel
• After the peripheral sends a burst request, the peripheral must not send a single request until the
DMAC acknowledges that the burst request is complete.
DMA Controller
Send Feedback
instruction - The DMAC waits for either a burst or single request from the peripheral.
instructions - The DMAC informs the peripheral when a transfer is complete.
register controls how much data is transferred for a burst request and a single request.
CCRn
.
n
DMAC Length Management
register when a transfer is in progress for
CCRn
16-17
Altera Corporation