Altera cyclone V Technical Reference page 1166

cv_5v4
2016.10.28
Peripheral
Quad SPI Flash Rx
STM
Reserved
UART 0 Tx
UART 0 Rx
UART 1 Tx
UART 1 Rx
Note: Request interface numbers 4 through 7 are multiplexed between the CAN controllers and soft logic
implemented in the FPGA fabric. The switching between the CAN controller and FPGA interfaces
is controlled by the system manager.
Mapping to a DMA Channel
The DMAC enables you to assign a peripheral request interface to any of the DMA channels. When a
DMA channel thread executes
peripheral associated with that DMA channel.
Related Information
DMAWFP
Request Acceptance Capability
During configuration of the DMAC, you can set the number of simultaneous active requests that a DMAC
is able to accept, for each peripheral request interface. An active request is where the DMAC has not
started the requested AXI data transfers.
The DMAC has a request FIFO, for each peripheral interface, which it uses to capture the requests from a
peripheral. The depth of a FIFO depends on the number of simultaneous active requests that the
corresponding peripheral request interface is configured to support. To store the state of an active request
from the peripheral, the request FIFO uses two bits to store the state of:
•
drtype_<x>[0]
•
drlast_<x>
When a request FIFO is full, then the DMAC sets the corresponding
the DMAC cannot accept any requests sent from the peripheral.
DMA Controller
Send Feedback
Request Interface
DMAWFP
on page 16-49
- Indicates the request type, burst or single
- Indicates if the peripheral is requesting the last data transfer of the DMA transfer
ID
25 ARM
26 ARM
27 N/A
28 Synopsys
29 Synopsys
30 Synopsys
31 Synopsys
, the value programmed in the peripheral [4:0] field specifies the
Mapping to a DMA Channel
Protocol
to LOW to signal that
drready_<x>
Altera Corporation
16-15