Cortex-A9 Microprocessor Unit Subsystem; Features Of The Cortex-A9 Mpu Subsystem; Interrupt Controller - Altera Cyclone V Device Handbook

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The hard processor system (HPS) in the Altera

microprocessor unit (MPU) subsystem is composed of a Cortex-A9 MPCore, a level 2 (L2) cache, an

Accelerator Coherency Port (ACP) ID mapper, and debugging modules.

The Altera Cortex-A9 MPU subsystem provides the following features:

• One or two Cortex-A9 processors

• Private interval and watchdog timer for each processor

• Global timer

• Symmetric multiprocessing (SMP) and asymmetric multiprocessing (AMP) modes

• Debugging modules

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Cortex-A9 Microprocessor Unit Subsystem

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, single- or dual-core 32-bit application processor. The Cortex-A9

system security extensions

SoC FPGA device includes a stand-alone, full-featured

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