Altera cyclone V Technical Reference page 1162

cv_5v4
2016.10.28
Figure 16-3: Request and Acknowledge Buses on the Peripheral Request Interface
Both buses use the valid and ready handshake that the AXI protocol describes.
The peripheral uses
• Request a single transfer
• Request a burst transfer
• Acknowledge a flush request
The peripheral uses
DMA transfer sequence.
The DMAC can indicate the following using
• When it completes the requested single transfer
• When it completes the requested burst transfer
• When it issues a flush request
Note: If you configure the DMAC to provide more than one peripheral request interface, each interface is
assigned a unique identifier,
For the Synopsys protocol, the following signals are used in the handshaking protocol:
•
dma_tx_req_n
•
dma_rx_req_n
•
dma_tx_ack_n
•
dma_rx_ack_n
•
dma_tx_single_n
•
dma_rx_single_n
Handshake Rules
The DMAC uses the DMA handshake rules that are listed, below, when a DMA channel thread is active,
that is, not in the Stopped state.
DMA Controller
Send Feedback
drvalid
drtype[1:0]
drlast
drready
Peripheral
davalid
datype[1:0]
daready
to either:
drtype[1:0]
to notify the DMAC that the request on
drlast
is transferred at the same time as
drlast
datype[1:0]
where
_<x>
Peripheral
Request DMAC
Interface
drtype[1:0]
drtype[1:0]
:
represents the number of the interface.
<x>
16-11
Handshake Rules
is the last request of the
.
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