Altera cyclone V Technical Reference page 1151

15-62
Document Revision History
Date
May 2016
May 2016
November 2015
May 2015
December 2014
July 2014
June 2014
February 2014
December 2013
November 2012
May 2012
January 2012
Altera Corporation
Version
2016.05.27
• Changed the name of the internal QSPI reference clock from
to
clk qspi_ref_clk
sclk_out
• Added a link to the Supported Flash Devices for Cyclone V and Arria
V SoC webpage.
• Re-worded information about disabling the watermark feature in
the "Indirect Read Operation" and "Indirect Write Operation"
sections.
2016.05.03
• Added clarification for the SRAM indirect read and write size
allocations.
• Updated the SRAM block on the "Quad SPI Flash Controller Block
Diagram and System Integration" figure.
2015.11.02
• Moved "Interface Signals" section below "Quad SPI Flash Controller
Block Diagram and System Integration"
• Better defined
• Updated step 11 in the "Setting Up the Quad SPI Flash Controller"
for clarity.
2015.05.04 Added information about clearing out the ECC before the feature is
enabled
2014.12.15 Maintenance release
2014.07.31 Updated address maps and register descriptions
2014.06.30
Added address maps and register definitions
2014.02.28 Maintenance release
2013.12.30 Maintenance release
1.2 Minor updates.
1.1 Added block diagram and system integration, functional description,
programming model, and address map and register definitions
sections.
1.0 Initial release.
Changes
; and the external QSPI output clock, from
to .
qspi_clk
clock.
l4_mp_clk
cv_5v4
2016.10.28
qspi_
Quad SPI Flash Controller
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