Altera cyclone V Technical Reference page 1164

cv_5v4
2016.10.28
Signal
daready
davalid
datype[1:0]
For more information, refer to the "Peripheral Request Interface Timing Diagrams" chapter.
Related Information
Peripheral Request Interface Timing Diagrams
Peripheral Request Interface Mapping
You can assign a peripheral request interface to any of the DMA channels. When a DMA channel thread
executes
DMAWFP
with that DMA channel.
The DMAC supports 32 peripheral request handshakes. Each request handshake can receive up to four
outstanding requests, and is assigned a specific peripheral device ID. The following table lists the
peripheral device ID assignments.
Table 16-3: Peripheral Request Interface Mapping
Peripheral
FPGA 0
FPGA 1
DMA Controller
Send Feedback
Indicates whether the peripheral can accept the information that the DMAC
provides on
datype_<x>[1:0]:
• 0 = peripheral not ready
• 1 = peripheral ready
Note: If
davalid
either it:
• Accepts a flush request from the DMAC
• Acknowledges the completion of a DMA transfer
Indicates when the DMAC provides valid control information:
• 0 = no control information is available
• 1 =
datype_<x>[1:0]
Note: The DMAC sets
control information on
remain constant until the peripheral sets
Indicates the type of acknowledgment, or request, that the DMAC signals:
• b00 = The DMAC has completed the single DMA transfer
• b01 = The DMAC has completed the burst DMA transfer
• b10 = DMAC requesting the peripheral to perform a flush request
• b11 = reserved
, the value programmed in the peripheral [4:0] field specifies the peripheral associated
Request Interface
ID
0
1
Peripheral Request Interface Mapping
Description
is HIGH, the peripheral sets
contains valid information for the peripheral
HIGH when it starts to provide valid
davalid
. The state of
datype
on page 16-19
Synopsys
Synopsys
HIGH when
daready
and
davalid datype
HIGH.
daready
Protocol
Altera Corporation
16-13