Altera cyclone V Technical Reference page 1163

16-12
Handshake Rules
•
drvalid
LOW when
•
drtype
•
drlast
•
davalid
LOW when
•
datype
Table 16-2: DMA Peripheral Interface Signal Definition
Signal
drready
drvalid
drtype[1:0]
drlast
Altera Corporation
can change from LOW to HIGH on any
is HIGH.
drready
can only change when either
can only change when either
can change from LOW to HIGH on any
is HIGH.
daready
can only change when either
Indicates whether the DMAC can accept the information that the peripheral
provides on
• 0 = DMAC not ready
• 1 = DMAC ready
Note: If
drvalid
when it accepts the peripheral request.
Indicates when the peripheral provides valid control information:
• 0 = No control information is available
• 1 =
drtype_<x>[1:0]
DMAC
Note: The peripheral sets
control information on
drlast
drready
Indicates the type of acknowledgment, or request, that the peripheral
signals:
• b00 = single level request
• b01 = burst level request
• b10 = acknowledging a flush request that the DMAC requested
• b11 = reserved
Indicates that the peripheral is sending the last data transfer for the current
DMA transfer:
• 0 = last data request is not in progress
• 1 = last data request is in progress
Note: The DMAC only uses this signal when
or b01.
cycle, but it must only change from HIGH to
aclk
is HIGH, or
drready drvalid
is HIGH, or
drready drvalid
cycle, but it must only change from HIGH to
aclk
is HIGH, OR
daready
Description
:
drtype_<x>[1:0]
is HIGH then the DMAC sets
and
drlast_<x>
HIGH when it starts to provide valid
drvalid
drlast
and must remain constant until the DMAC sets
drtype
HIGH.
is LOW.
is LOW.
is LOW.
davalid
to HIGH
drready
contain valid information for the
and . The state of
drtype
drtype_<x>[1:0]
cv_5v4
2016.10.28
,
drvalid
is b00
DMA Controller
Send Feedback