Clock Circuitry; On-Board Oscillators - Altera Arria V GX Reference Manual

2–20

Clock Circuitry

On-Board Oscillators

Figure 2–7. Arria V GX Starter Board Clocks
Si510 SE
50 MHz Fixed
Oscillator
Table 2–14. On-Board Oscillators
Source
X4
X3
Arria V GX Starter Board
Reference Manual
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This section describes the board's clock inputs and outputs.
The starter board includes programmable oscillators with a frequency of 100-MHz,
125-MHz, 156.25-MHz, and 409.60-MHz.
Figure 2–7 shows the default frequencies of all external clocks going to the Arria V GX
starter board.
DDR3 x32 UniOHY, User I/O
Bank
CH0
HSMC x8
R1
Si5338
Arria V FPGA
CH2
Bank
HDMI x3
Si5338
R0
User I/O, HSMC VIO, Enet, HDMI
Enet
Si511
125.0 MHz LVDS
Fixed Oscillator
SL18860DC
Clock Fan-Out
x4 SE 50 MHz
System Controller
Table 2–14 lists the oscillators, its I/O standard, and voltages required for the starter
board.
Schematic Signal Name Frequency
CLKIN_50_TOP
50.000 MHz
CLKIN_50_BOT
CLKIN_50_MAXV
100.000 MHz
CLLK_CONFIG
Trigger Out
SMA
LVDS VCXO
148.5 MHz and
148.35 MHz
Bank
SMA x1
L1
SDI x1
Bank
PCIe x8
L0
Si510 SE
MAX V CPLD
50 MHz Fixed
Oscillator
FA-128
24.0 MB-W
24 MHz XTAL
I/O Standard
2.5V CMOS
2.5V CMOS
Chapter 2: Board Components
Si571
Bank Top
Bank Bottom
IDT5T9306
Clock Fan-Out
Bank L1
x4 LVDS
Bank R1
2 Unused Channels
Bank R0
NB6L11SMNG
Clock Fan-Out
x2 LVDS
100 MHz
SG-310DF 10/100/1000
25.0 M-B3
Base-T
25 MHz Ethernet PHY
Fixed Oscillator 88E1111
CY7C68013A
MAX II CPLD
USB
Embedded
Microcontroller
USB-Blaster
Arria V GX Pin
Application
Number
A16
AP29 Nios II and MAX V
—
— Fast FPGA configuration
September 2015 Altera Corporation
Clock Circuitry
SMA
LVPECL
Clock input
SMA SMA
Si5338
x4 LVDS Output
CH0 125 MHz
CH1 409.6 MHz
CH2 156.25 MHz
CH3 100 MHz