Clock Circuitry - Altera DE2-115 User Manual

HEX7[2]
HEX7[3]
HEX7[4]
HEX7[5]
HEX7[6]
4 . 5 C l o c k C i
4 . 5 C l o c k C i
The DE2-115 board includes one oscillator that produces 50 MHz clock signal. A clock buffer is
used to distribute 50 MHz clock signal with low jitter to FPGA. The distributing clock signals are
connected to the FPGA that are used for clocking the user logic. The board also includes two SMA
connectors which can be used to connect an external clock source to the board or to drive a clock
signal out through the SMA connector. In addition, all these clock inputs are connected to the phase
locked loops (PLL) clock input pins of the FPGA to allow users to use these clocks as a source
clock for the PLL circuit.
The clock distribution on the DE2-115 board is shown in
assignments for clock inputs to FPGA I/O pins are listed in
Signal Name
CLOCK_50
CLOCK2_50
CLOCK3_50
SMA_CLKOUT
SMA_CLKIN
PIN_AG17 Seven Segment Digit 7[2]
PIN_AH17 Seven Segment Digit 7[3]
PIN_AF17 Seven Segment Digit 7[4]
PIN_AG18 Seven Segment Digit 7[5]
PIN_AA14 Seven Segment Digit 7[6]
r c u i t r y
r c u i t r y
Figure 4-11 Block diagram of the clock distribution
Table 4-5 Pin Assignments for Clock Inputs
FPGA Pin No.
PIN_Y2
PIN_AG14
PIN_AG15
PIN_AE23
PIN_AH14
Figure
Table
Description
50 MHz clock input
50 MHz clock input
50 MHz clock input
External (SMA) clock output
External (SMA) clock input
38
Depending on JP6
Depending on JP6
Depending on JP6
Depending on JP6
3.3V
4-11. The associated pin
4-5.
I/O Standard
3.3V
3.3V
Depending on JP6
Depending on JP6
3.3V