Address Clock Enable Support - Altera Cyclone IV Device Handbook

Chapter 3: Memory Blocks in Cyclone IV Devices
Overview

Address Clock Enable Support

Cyclone IV devices M9K memory blocks support an active-low address clock enable,
which holds the previous address value for as long as the addressstall signal is high
(addressstall = '1'). When you configure M9K memory blocks in dual-port mode,
each port has its own independent address clock enable.
Figure 3–2
feeds back to its input using a multiplexer. The multiplexer output is selected by the
address clock enable (addressstall) signal.
Figure 3–2. Cyclone IV Devices Address Clock Enable Block Diagram
The address clock enable is typically used to improve the effectiveness of cache
memory applications during a cache-miss. The default value for the address clock
enable signals is low.
November 2011 Altera Corporation
shows an address clock enable block diagram. The address register output
address[0]
address[N]
addressstall
clock
address[0]
address[0]
register
address[N]
address[N]
register
Cyclone IV Device Handbook,
3–5
Volume 1