Functional Description Of The Clock Manager; Clock Manager Building Blocks - Altera Cyclone V Device Handbook

cv_54002
2013.12.30
Figure 2-1: Clock Manager Block Diagram
f2h_sdram_ref_clk
HPS_CLK2
HPS_CLK1
Reset
Manager

Functional Description of the Clock Manager

Clock Manager Building Blocks

PLLs
The clock manager contains three PLLs: main, peripherals, and SDRAM. These PLLs generate the majority
of clocks in the HPS. There is no phase control between the clocks generated by the three PLLs.
Each PLL has the following features:
• Phase detector and output lock signal generation
• Registers to set VCO frequency
• Multiplier range is 1 to 4096
• Divider range is 1 to 64
• Six post-scale counters (C0-C5) with a range of 1 to 512
• PLL can be enabled to bypass all outputs to the osc1_clk clock for glitch-free transitions
Clock Manager
Send Feedback
f2h_periph_ref_clk
Main Clock Group
Main
PLL
Peripheral Clock Group
Peripheral
PLL
SDRAM Clock Group
SDRAM
PLL
OSC1 Clock Group
reset_manager_safe_mode_req
Functional Description of the Clock Manager
FPGA Portion
Clock Manager
Dividers
Dividers
osc1_clk
Control
Logic
L4 Bus (osc1_clk)
Flash Controller Clocks
Divider
Control & Status
Registers
2-3
Flash
Controllers
MPU, L3, L4
& Debug
PLL-Driven
Peripherals
SDRAM
Controller
Subsystem
OSC1-Driven
Peripherals
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