I/O Features; Clock Management; External Memory Interfaces - Altera Cyclone IV Device Handbook

Chapter 1: Cyclone IV FPGA Device Family Overview
Cyclone IV Device Family Architecture

I/O Features

Cyclone IV device I/O supports programmable bus hold, programmable pull-up
resistors, programmable delay, programmable drive strength, programmable
slew-rate control to optimize signal integrity, and hot socketing. Cyclone IV devices
support calibrated on-chip series termination (Rs OCT) or driver impedance matching
(Rs) for single-ended I/O standards. In Cyclone IV GX devices, the high-speed
transceiver I/Os are located on the left side of the device. The top, bottom, and right
sides can implement general-purpose user I/Os.
Table 1–8
Table 1–8. I/O Standards Support for the Cyclone IV Device Family
Single-Ended I/O
Differential I/O
The LVDS SERDES is implemented in the core of the device using logic elements.
f
For more information, refer to the

Clock Management

Cyclone IV devices include up to 30 global clock (GCLK) networks and up to eight
PLLs with five outputs per PLL to provide robust clock management and synthesis.
You can dynamically reconfigure Cyclone IV device PLLs in user mode to change the
clock frequency or phase.
Cyclone IV GX devices support two types of PLLs: multipurpose PLLs and general-
purpose PLLs:
Use multipurpose PLLs for clocking the transceiver blocks. You can also use them
■
for general-purpose clocking when they are not used for transceiver clocking.
■ Use general purpose PLLs for general-purpose applications in the fabric and
periphery, such as external memory interfaces. Some of the general purpose PLLs
can support transceiver clocking.
f
For more information, refer to the
chapter.

External Memory Interfaces

Cyclone IV devices support SDR, DDR, DDR2 SDRAM, and QDRII SRAM interfaces
on the top, bottom, and right sides of the device. Cyclone IV E devices also support
these interfaces on the left side of the device. Interfaces may span two or more sides of
the device to allow more flexible board design. The Altera
interface solution consists of a PHY interface and a memory controller. Altera supplies
the PHY IP and you can use it in conjunction with your own custom memory
controller or an Altera-provided memory controller. Cyclone IV devices support the
use of error correction coding (ECC) bits on DDR and DDR2 SDRAM interfaces.
March 2016 Altera Corporation
lists the I/O standards that Cyclone IV devices support.
Type
LVTTL, LVCMOS, SSTL, HSTL, PCI, and PCI-X
SSTL, HSTL, LVPECL, BLVDS, LVDS, mini-LVDS, RSDS, and PPDS
I/O Standard
I/O Features in Cyclone IV Devices
Clock Networks and PLLs in Cyclone IV Devices
®
1–9
chapter.
DDR SDRAM memory
Cyclone IV Device Handbook,
Volume 1