Clock Manager; Features Of The Clock Manager - Altera Cyclone V Device Handbook

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The hard processor system (HPS) clock generation is centralized in the clock manager. The clock manager

is responsible for providing software-programmable clock control to configure all clocks generated in the

HPS. Clocks are organized in clock groups. A clock group is a set of clock signals that originate from the

same clock source. A phase-locked loop (PLL) clock group is a clock group where the clock source is a

common PLL voltage-controlled oscillator (VCO).

The clock manager offers the following features:

• Generates and manages clocks in the HPS

• Contains the following PLL clock groups:

• Main contains clocks for the Cortex

interconnect, level 4 (L4) peripheral bus, and debug

• Peripheral contains clocks for PLL-driven peripherals

• SDRAM contains clocks for the SDRAM subsystem

• Allows scaling of the MPU subsystem clocks without disabling peripheral and SDRAM clock groups

• Generates clock gate controls for enabling and disabling most clocks

• Initializes and sequences clocks for the following events:

• Cold reset

• Safe mode request from reset manager on warm reset

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-A9 microprocessor unit (MPU) subsystem, level 3 (L3)

Clock Manager

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