Max V Cpld 5M2210 System Controller - Altera Arria V GX Reference Manual

Chapter 2: Board Components

MAX V CPLD 5M2210 System Controller

MAX V CPLD 5M2210 System Controller
Figure 2–4. MAX V CPLD 5M2210 System Controller Block Diagram
PC
On-Board
USB-Blaster II
Power
Measurement
Results
Table 2–5. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 1 of 6)
Board
Reference (U15)
N4
B9
E9
J5
A15
A13
J12
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The board utilizes the 5M2210 System Controller, an Altera MAX V CPLD, for the
following purposes:
■ FPGA configuration from flash
■ Power measurement
■ Fan control (shared with the FPGA)
Control registers for clocks
■
■ Control and status registers for remote system update
Figure 2–4 illustrates the MAX V CPLD 5M2210 System Controller's functionality and
external circuit connections as a block diagram.
JTAG Control
SLD-HUB
Virtual-JTAG
Encoder
LTC2418
Controller
Table 2–5 lists the I/O signals present on the MAX V CPLD 5M2210 System
Controller. The signal names and functions are relative to the MAX V device (U15).
Schematic Signal Name I/O Standard
5M2210_JTAG_TMS
CLK125_EN
CLK50_EN
CLK_CONFIG
CLK_ENABLE
CLK_SEL
CLKIN_50_MAXV
MAX V CPLD System Controller
Information
Register
Control
Register
Decoder
PFL
Si571
Controller
Si5538
Controller
2.5-V MAX V JTAG TMS
2.5-V 125 MHz oscillator enable
2.5-V 50 MHz oscillator enable
2.5-V 100 MHz configuration clock input
2.5-V DIP switch for clock oscillator enable
2.5-V DIP switch for clock select—SMA or oscillator
2.5-V 50 MHz clock input
FSM BUS
FPGA
Flash
Flash
SSRAM
GPIO
Si571
Programmable
Oscillator
Si5338
Programmable
Oscillator
Description
Arria V GX Starter Board
Reference Manual
2–7