Max Ii Cpld Epm2210 System Controller - Altera Cyclone IV GX Reference Manual

2–6

MAX II CPLD EPM2210 System Controller

Figure 2–3. MAX II CPLD EPM2210 System Controller Block Diagram
PC
MAX II
Embedded
USB-Blaster
Power
Measurement
Results
Table 2–5. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 1 of 3)
Schematic Signal Name
CLK125_EN
CLK125_SDA
CLK125_SCK
CLK_SEL
CLK_MAXII
EPCS_nCS
FLASH_CEn
FSML_OEn
Cyclone IV GX Transceiver Starter Board Reference Manual
Downloaded from Elcodis.com electronic components distributor
The board utilizes the EPM2210 System Controller, an Altera MAX II CPLD, for the
following purposes:
■ FPGA configuration from flash memory
■ Power consumption monitoring
Virtual JTAG interface for PC-based GUI
■
■ Control registers for clocks
■ Control registers for remote system update
Figure 2–3 illustrates the MAX II CPLD EPM2210 System Controller's functionality
and external circuit connections as a block diagram.
JTAG Control
SLD-HUB
Virtual-JTAG
Encoder
LTC2418
Controller
Power
Calculations
Table 2–5 lists the I/O signals present on the MAX II CPLD EPM2210 System
Controller. The signal names and functions are relative to the MAX II device (U10).
I/O EPM2210
Standard Pin Number
R1
T2
R3
R4
2.5-V
J5
B13
A2
B1
Information
Register
Decoder
Control
Register
PFL
MAX II CPLD EPM2210 System Controller
EP4CGX15BF14
Pin Number
— 125-MHz oscillator enable
— 125-MHz programming data
— 125-MHz programming clock
— DIP - clock select SMA or oscillator
— MAX II clock input
C5 EPCS memory chip enable
B8 FSML bus flash memory chip enable
B13 FSML bus flash memory output enable
Chapter 2: Board Components
MAX II CPLD EPM2210 System Controller
EP4CGX15
FLASH
SSRAM
LCD
GPIO
Description
© March 2010 Altera Corporation