Interconnect Block Diagram And System Integration - Altera Cyclone V Device Handbook

4-2

Interconnect Block Diagram and System Integration

Interconnect Block Diagram and System Integration
Figure 4-1: Interconnect Block Diagram and System Integration
The following figure shows a block diagram of the L3 interconnect and L4 buses. For L3 main switch
connection details, refer to
32-Bit APB Bus
(L4_MP, l4_mp_clk)
GPIO
(3)
S
DAP
S M
ETR
32-Bit AXI
(dbg_at_clk)
M
SD/MMC
32-Bit AHB
(l4_mp_clk)
S M
EMAC
32-Bit AXI
(2)
(l4_mp_clk)
S M
USB
32-Bit AHB
OTG
(usb_mp_clk)
(2) M
S
32-Bit AXI
NAND
(nand_x_clk)
S M
S
32-Bit AXI
(nand_x_clk)
32-Bit AXI (nand_x_clk)
32-Bit AHB (usb_mp_clk)
32-Bit APB (l4_mp_clk)
S S
32-Bit AHB
Quad SPI
(l4_mp_clk)
Flash
(L4_OSC1, osc1_clk)
S
System
Manager
The L3 interconnect is a partially-connected switch fabric. Not all masters can access all slaves.
Altera Corporation
Table 4-1.
S
FPGA
Manager
S
32-Bit AXI
(cfg_clk)
L3 Interconnect
M
(NIC-301)
32-Bit AHB (dbg_clk)
S (GPV)
L3 Master
Peripheral
Switch
S
l3_mp_clk
S
32-Bit AXI
(l3_mp_clk)
M S
S
S
32-Bit AXI
S
(l3_sp_clk)
L3 Slave Peripheral Switch
l3_sp_clk
M
M
M
M
M
M
32-Bit APB Bus
S S S S
OSC1 Watchdog Clock Reset
Timer (2) (2) Manager Manager
Lightweight
FPGA-to-HPS HPS-to-FPGA HPS-to-FPGA Bridge
Bridge Bridge
S
(GPV)
M S
64-Bit AXI 64-Bit AXI
32-Bit AXI
(l3_main_clk) (l3_main_clk)
(l4_mp_clk)
S M
(GPV)
64-Bit AXI
(mpu_l2_ram_clk)
M
(1)
L3 Main Switch
l3_main_clk
64-Bit AXI
(mpu_l2_ram_clk)
(GPV) S
32-Bit AXI
(dbg_at_clk)
M
32-Bit AXI
(l3_main_clk)
M
64-Bit AXI
(l3_main_clk)
M
32-Bit AXI (l3_main_clk)
M
M S
S
M
32-Bit APB (l4_main_clk)
M
M M
32-Bit APB Bus
(L4_SPI_M, spi_m_clk)
S
S S
Scan SPI SP
Manager Master (2) Timer (2)
MPU Subsystem
(mpu_clk)
ACP ID
64-Bit AXI
Mapper
(mpu_l2_ram_clk)
S M S ACP
S
64-Bit AXI
(mpu_clk)
STM
S
Boot
S
ROM
On-Chip
S
RAM
DMA
M
64-Bit AXI
(l4_main_clk)
S
S
32-Bit APB Bus
SPI Slave (L4_MAIN,
(2) l4_main_clk)
S
32-Bit APB Bus
(L4_SP, I4_sp_clk)
S S S
2
I C UART CAN
(4) (2) (2)
cv_54004
2013.12.30
Legend
M: Master
S: Slave
Switch Connection
ARM Cortex-A9
MPCore
CPU0 CPU1
SCU
M M
64-Bit AXI
(mpu_clk)
S S
L2
Cache
M
M
64-Bit AXI
(mpu_l2_ram_clk)
S
SDRAM
S
Controller
Subsystem
S
Interconnect
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