External Clock Output Select Jumper (J23); Clocks; External Clock Input Sma Connectors (J26, J30) - Altera HSMC Reference Manual

2–6

External Clock Output Select Jumper (J23)

Table 2–8
Table 2–8. External Clock Output Select Jumper (J23) Settings
Clock Source
FPGA Clock
FPGA Clock
A/D A DCO
A/D B DCO
Note to Table 2–8:
(1) On the schematic, MUX (U13) output signal names are RX_CLK_P and RX_CLK_N.

Clocks

This section describes the external clock input and output SMA connectors.

External Clock Input SMA Connectors (J26, J30)

The CLK SMA connector (J26 or J30) provides an external clock input. It can be
selected to be the input to U1, U2, and U3
provides (while using a particular design) the flexibility to use the same external clock
source for the entire system under test. If you choose to use a single-ended clock, R112
must be removed and R111 be installed.
Figure 2–3. External Clock Input Schematic
External Clock In
J26 LTI-SASF54GT
1 XT_CK_IN_P
5 4 3 2
J30
XT_CK_IN_N
1
5 4 3 2
LTI-SASF54GT
Data Conversion HSMC Reference Manual
lists the external clock output select jumper (J23) settings.
Board Reference
HSMC Connector
FPGA_CLK_A_P
FPGA_CLK_A_N
HSMC Connector
FPGA_CLK_B_P
FPGA_CLK_B_N
A/D Channel A
ADA_DCO_P
ADA_DCO_N
A/D Channel B
ADB_DCO_P
ADB_DCO_N
XT_CK_IN_UNI
Unipolar
R111 XT_CK_IN_BI
0
R112
Bipolar
0
Chapter 2: Board Components and Interfaces
Schematic Signal Name
(1)
(Figure 2–3). An external clock input
T6
P S
4 3
VTT_XCK
5 2
6 1
TT1_8_KK91
External Clock Output Select
Jumper (J23) Settings
Pins 3 and 5
Pins 4 and 6
Pins 1 and 3
Pins 4 and 6
Pins 3 and 5
Pins 2 and 4
Pins 1 and 3
Pins 2 and 4
3.3 V
R75
1.00K, 1%
XT_IN_P
XT_IN_N
C70
R78
0.1µF
1.00K, 1%
© November 2008 Altera Corporation
Clocks