Software And Hardware Requirements - Altera Nios II Hardware Development Manual

1–2
Figure 1–1
target board, the FPGA, and the Nios II system.
Figure 1–1. Tutorial Design Example
Target Board
Altera FPGA
10-pin
JTAG
header
Clock
oscillator
As shown in
system. In fact, most FPGA designs with a Nios II system also include other logic. A
Nios II system can interact with other on-chip logic, depending on the needs of the
overall system. For the sake of simplicity, the design example in this tutorial does not
include other logic in the FPGA.

Software and Hardware Requirements

This tutorial requires you to have the following software:
■ Altera Quartus II software version 11.0 or later—The software must be installed on
a Windows or Linux computer that meets the Quartus II minimum requirements.
f
■ Nios II EDS version 11.0 or later.
Design files for the design example—A hyperlink to the design files appears next
■
to this document on the
Nios II Hardware Development Tutorial
is a block diagram showing the relationship among the host computer, the
Nios II System
Debug
Instr
control
Nios II/s
Data
core
JTAG
UART
Character
I/O
Timer
Other logic
Figure 1–1, other logic can exist within the FPGA alongside the Nios II
For system requirements and installation instructions, refer to
Software Installation and
Literature: Nios II Processor
Chapter 1: Nios II Hardware Development
8
PIO
System
ID
On-chip
RAM
Licensing.
page of the Altera website.
Software and Hardware Requirements
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Altera
May 2011 Altera Corporation