Hardware-Managed And Software-Managed Clocks; Clock Groups - Altera Cyclone V Device Handbook

cv_54002
2013.12.30
Clock Gating
Clock gating enables and disables clock signals.
Control and Status Registers
The clock manager contains registers used to configure and observe the clock manager.

Hardware-Managed and Software-Managed Clocks

When changing values on clocks, the terms hardware-managed and software-managed define who is
responsible for successful transitions. Software-managed clocks require that software manually gate off any
clock affected by the change, wait for any PLL lock if required, then gate the clocks back on. Hardware-
managed clocks use hardware to ensure that a glitch-free transition to a new clock value occurs. There are
three hardware-managed sets of clocks in the HPS, namely, clocks generated from the main PLL outputs
C0, C1, and C2. All other clocks in the HPS are software-managed clocks.

Clock Groups

The clock manager contains one clock group for each PLL and one clock group for the EOSC1 pin.
OSC1 Clock Group
The clock in the OSC1 clock group is derived directly from the EOSC1 pin. This clock is never gated or
divided.
It is used as a PLL input and also by HPS logic that does not operate on a clock output from a PLL.
Table 2-1: OSC1 Clock Group Clock
Name
osc1_clk
Main Clock Group
The main clock group consists of a PLL, dividers, and clock gating. The clocks in the main clock group are
derived from the main PLL. The main PLL is always sourced from the EOSC1 pin of the device.
Clock Manager
Send Feedback
Frequency
10 to 50 MHz
Clock Source
EOSC1 pin
2-5
Clock Gating
Destination
OSC1-driven
peripherals listed in
Table 2–9 on page 2–14
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