Dynamic Reconfiguration Controller Architecture - Altera Cyclone IV Device Handbook

3–2
Table 3–1. Glossary of Terms Used in this Chapter (Part 2 of 2)
Term
Memory Initialization File,
also known as .mif
PMA controls
Transceiver channel

Dynamic Reconfiguration Controller Architecture

The dynamic reconfiguration controller is a soft intellectual property (IP) that utilizes
FPGA-fabric resources. You can use only one controller per transceiver block. You
cannot use the dynamic reconfiguration controller to control multiple Cyclone IV
devices or any off-chip interfaces.
Cyclone IV Device Handbook,
Volume 2
A file with the .mif extension will be generated for .mif-based reconfiguration mode. It can
be either in Channel Reconfiguration mode or PLL Reconfiguration mode.
Channel Reconfiguration mode—this file contains information about the various ALTGX
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MegaWizard Plug-In Manager options that you set. Each word in the .mif is 16 bits wide.
The dynamic reconfiguration controller writes information from the .mif into the
transceiver channel.
PLL Reconfiguration mode—this file contains information about the various PLL
■
parameters and settings that you use to configure the transceiver PLL to different output
frequency. The .mif file is 144  1-bit size. During PLL reconfiguration mode, the PLL
reconfiguration controller shifts these 144-bit serially into the transceiver PLL.
Represents analog controls (Voltage Output Differential [V
and Manual Equalization) as displayed in both the ALTGX and ALTGX_RECONFIG
MegaWizard Plug-In Managers.
Refers to a transmitter channel, a receiver channel, or a duplex channel that has both PMA
and PCS blocks.
Chapter 3: Cyclone IV Dynamic Reconfiguration
Dynamic Reconfiguration Controller Architecture
Description
], Pre-emphasis, DC Gain,
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November 2011 Altera Corporation