Internal Dma Controller Operations - Altera Cyclone V Device Handbook

cv_54011
2013.12.30
• Set the command index to 0x52 (IO_RW_DIRECT).
• Set the stop_abort_cmd bit of the cmd register to 1 to inform the controller that the host aborted
the data transfer.
• Set the wait_prvdata_complete bit of the cmd register to 0.
3. Wait for the cmd bit in the rintsts register to change to 1.
4. Read the response to the IO_RW_DIRECT command (R5) in the response registers for any errors.
For more information about response values, refer to the Physical Layer Simplified Specification, Version
3.01, available on the SD Association website.
Related Information
www.sdcard.org
To learn more about how SD technology works, visit the SD Association website.
cmdarg Register Settings for SD/SDIO ABORT Command
Table 11-21: cmdarg Register Settings for SD/SDIO ABORT Command
Bits
31
30:28
27
26
25:9
8
7:0

Internal DMA Controller Operations

For better performance, you can use the internal DMA controller to transfer data between the host and the
controller. This section describes the internal DMA controller's initialization process, and transmission
sequence, and reception sequence.
Internal DMA Controller Initialization
To initialize the internal DMA controller, perform the following steps:
1. Set the required bmod register bits:
SD/MMC Controller
Send Feedback
cmdarg Register Settings for SD/SDIO ABORT Command
†
Contents
R/W flag
Function number
RAW flag
Don't care
Register address
Don't care
Write data
†
†
†
†
†
Value
1
0, for access to the CCCR in the card device
1, if needed to read after write
0x06
Function number to abort
†
†
11-45
†
-
-
Altera Corporation