System Manager Block Diagram And System Integration - Altera Cyclone V Device Handbook

14-2

System Manager Block Diagram and System Integration

System Manager Block Diagram and System Integration
The system manager connects to the level 4 bus through a slave interface. The CSRs connect to signals in
the FPGA and also to other HPS modules.
Figure 14-1: System Manager Block Diagram
The system manager consists of the following blocks:
• CSRs Provide memory-mapped access to control signals for the following HPS modules:
• EMACs
• Debug core
• SD/MMC controller
• NAND controller
• USB controllers
• DMA controller
• L3 Interconnect
• Route ECC and parity interrupts to the MPU
• Store status information received from other HPS modules
• Register slave interface provides connected masters access to the CSRs in the system manager.
• Watchdog debug pause accepts the debug mode status from the MPU subsystem and pauses the L4
watchdog timers.
Altera Corporation
System Manager
Register
Slave
Interface
HPS BSEL pins
Pause
L4 Watchdog Timers
Watchdog
Debug Status
Debug Pause
Parity Injection
ECC & Parity
Interrupts
Memory-Mapped
Control Signals
CSRs
ECC Status
Signals
FPGA JTAG Control
FPGA
Control
FPGA
Block
Fabric
MPU
Logic with
Parity RAM
Generic Interrupt
Controller
(1)
Other Modules
Modules with
ECC RAM
System Manager
Send Feedback
cv_54014
2013.12.30