Reset; Fpga Manager Address Map And Register Definitions; Document Revision History - Altera Cyclone V Device Handbook

13-8

Reset

Reset
The FPGA manager has one reset signal. The reset manager drives this signal to FPGA manager on a cold
or warm reset. All distributed reset signals in the FPGA manager are asserted asynchronously at the same
time and de-asserted synchronously to their associated clocks.
Related Information
Reset Manager

FPGA Manager Address Map and Register Definitions

The address map and register definitions reside in the hps.html file that accompanies this handbook volume.
Click the link to open the file.
To view the module description and base address, scroll to and click the following links for the module
instance:
• fpgamgrregs
• fpgamgrdata
To then view the register and field descriptions, scroll to and click the register names. The register addresses
are offsets relative to the base address of each module instance.
Related Information
• Introduction to Cyclone V Hard Processor System (HPS)
• Cyclone V SoC HPS Address Map and Register Definitions

Document Revision History

Table 13-2: Document Revision History
Date
December 2013
November 2012
June 2012
May 2012
January 2012
Altera Corporation
on page 3-1
2013.12.30
1.3
1.2
1.1
1.0
on page 1-1
Version
Minor updates.
Minor updates.
Updated the FPGA configuration
section.
• Updated the configuration
• Updated the FPGA configura-
• Added address map and
Initial release.
Changes
schemes table.
tion section.
register definitions section.
FPGA Manager
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2013.12.30