Hps-Fpga Axi Bridges Address Map And Register Definitions; Document Revision History - Altera Cyclone V Device Handbook

cv_54005
2013.12.30
1. DECERR
2. SLVERR
3. OKAY

HPS-FPGA AXI Bridges Address Map and Register Definitions

The address map and register definitions reside in the hps.html file that accompanies this handbook volume.
Click the link below to open the file.
To view the module description and base address, scroll to and click the following links for the module
instance:
• fpga2hpsregs
• hps2fpgaregs
To then view the register and field descriptions, scroll to and click the register names. The register addresses
are offsets relative to the base address of each module instance.
Related Information
• Introduction to Cyclone V Hard Processor System (HPS)
The base addresses of all modules are also listed in the Introduction to the Hard Processor chapter.
• hps.html

Document Revision History

Table 5-21: Document Revision History
Date
December 2013
November 2012
January 2012
HPS-FPGA AXI Bridges
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HPS-FPGA AXI Bridges Address Map and Register Definitions
Version
2013.12.30
1.1
1.0
on page 1-1
Changes
Maintenance release.
Described GPV.
Initial release.
5-15
Altera Corporation