Jtag Debug Module - Altera Nios II User Manual

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■ Read and write access permissions for data regions
■ Execute access permissions for instruction regions
Overlapping regions
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f
For more information about the MPU implementation, refer to the
chapter of the Nios II Processor Reference Handbook.
You can optionally include the MPU when you instantiate the Nios II processor in
your Nios II hardware system. When present, the MPU is always enabled. Several
parameters are available, allowing you to optimize the MPU for your system needs.
f
For complete details about user-selectable parameters for the Nios II MPU, refer to the
Instantiating the Nios II Processor
1
The Nios II MPU is optional and mutually exclusive from the Nios II MMU. Nios II
systems can include either an MPU or MMU, but cannot include both an MPU and
MMU on the same Nios II processor core.

JTAG Debug Module

The Nios II architecture supports a JTAG debug module that provides on-chip
emulation features to control the processor remotely from a host PC. PC-based
software debugging tools communicate with the JTAG debug module and provide
facilities, such as the following features:
Downloading programs to memory
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■ Starting and stopping execution
■ Setting breakpoints and watchpoints
■ Analyzing registers and memory
Collecting real-time execution trace data
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1
The debug module connects to the JTAG circuitry in an Altera FPGA. External
debugging probes can then access the processor via the standard JTAG interface on
the FPGA. On the processor side, the debug module connects to signals inside the
processor core. The debug module has nonmaskable control over the processor, and
does not require a software stub linked into the application under test. All system
resources visible to the processor in supervisor mode are available to the debug
module. For trace data collection, the debug module stores trace data in memory
either on-chip or in the debug probe.
The debug module gains control of the processor either by asserting a hardware break
signal, or by writing a break instruction into program memory to be executed. In both
cases, the processor transfers execution to the routine located at the break address.
The break address is specified with the Nios II Processor parameter editor in Qsys.
Nios II Processor Reference Handbook
chapter of the Nios II Processor Reference Handbook.
The Nios II MMU does not support the JTAG debug module trace.
Chapter 2: Processor Architecture
JTAG Debug Module
Programming Model
February 2014 Altera Corporation