Upsizing Data Width Function - Altera Cyclone V Device Handbook

cv_54004
2013.12.30
Slave
NAND CSR
NAND command and
data
Quad SPI flash data
FPGA manager data
HPS-to-FPGA bridge
ACP ID mapper data
STM
On-chip boot ROM
On-chip RAM
SDRAM subsystem L3
data

Upsizing Data Width Function

The upsizing function combines narrow transactions into wider transactions to increase the overall system
bandwidth. Upsizing only packs data for read or write transactions that are cacheable. If the interconnect
splits input-exclusive transactions into more than one output bus transaction, it removes the exclusive
information from the multiple transactions it creates.
The upsizing function can expand the data width by the following ratios:
• 1:2
• 1:4
If multiple responses from created transactions are combined into one response, then the following order
of priority applies:
• DECERR is the highest priority
• SLVERR is the next highest priority
• OKAY is the lowest priority.
Related Information
infocenter.arm.com
For more information about AXI terms such as DECERR, WRAP, and INCR, refer to the AMBA AXI Protocol
Specification v1.0, which you can download from the ARM website.
Interconnect
Send Feedback
Interface Clock
Width
32
nand_x_clk
32
nand_x_clk
32
l4_mp_clk
32
cfg_clk
64
l3_main_clk
64
mpu_l2_ram_
clk
32
dbg_at_clk
32
l3_main_clk
64
l3_main_clk
32
l3_main_clk
Upsizing Data Width Function
Mastered By Acceptance
L3 slave peripheral 1, 1, 1
switch
L3 slave peripheral 1, 1, 1
switch
L3 slave peripheral 1, 1, 1
switch
L3 main switch 1, 2, 3
L3 main switch 16, 16, 32
L3 main switch 13, 5, 18
L3 main switch 1, 2, 2
L3 main switch 1, 1, 2
L3 main switch 2, 2, 2
L3 main switch 16, 16, 16
4-17
Buffer Interface
Depth Type
2, 2, 2 AXI
2, 2, 2 AXI
2, 2, 2 AHB
2, 2, 2, 32, AXI
2
2, 2, 6, 6, 2 AXI
2, 2, 2, 2, 2 AXI
2, 2, 2, 2, 2 AXI
0, 0, 0, 0, 0 AXI
0, 0, 0, 8, 0 AXI
2, 2, 2, 2, 2 AXI
Altera Corporation