Memory And Peripheral Access - Altera Nios II User Manual

Chapter 3: Programming Model

Memory and Peripheral Access

Masking Interrupts with the Internal Interrupt Controller
The ienable register controls the handling of internal hardware interrupts. Each bit of
the ienable register corresponds to one of the interrupt inputs, irq0 through irq31. A
value of one in bit n means that the corresponding irqn interrupt is enabled; a bit
value of zero means that the corresponding interrupt is disabled. Refer to
Processing" on page 3–31
An ISR can adjust ienable so that IRQs of equal or lower priority are disabled. Refer
to "Handling Nested Exceptions" on page 3–50
Memory and Peripheral Access
Nios II addresses are 32 bits, allowing access up to a 4-gigabyte address space. Nios II
core implementations without MMUs restrict addresses to 31 bits or fewer. The MMU
supports the full 32-bit physical address.
f
For details, refer to the
Processor Reference Handbook.
Peripherals, data memory, and program memory are mapped into the same address
space. The locations of memory and peripherals within the address space are
determined at system generation time. Reading or writing to an address that does not
map to a memory or peripheral produces an undefined result.
The processor's data bus is 32 bits wide. Instructions are available to read and write
byte, half-word (16-bit), or word (32-bit) data.
The Nios II architecture uses little-endian byte ordering. For data wider than 8 bits
stored in memory, the more-significant bits are located in higher addresses.
The Nios II architecture supports register+immediate addressing.
Cache Memory
The Nios II architecture and instruction set accommodate the presence of data cache
and instruction cache memories. Cache management is implemented in software by
using cache management instructions. Instructions are provided to initialize the
cache, flush the caches whenever necessary, and to bypass the data cache to properly
access memory-mapped peripherals.
The Nios II architecture provides the following mechanisms to bypass the cache:
When no MMU is present, bit 31 of the address is reserved for bit-31 cache bypass.
■
With bit-31 cache bypass, the address space of processor cores is 2 GB, and the
high bit of the address controls the caching of data memory accesses.
■ When the MMU is present, cacheability is controlled by the MMU, and bit 31
functions as a normal address bit. For details, refer to
Memory Partitions" on page
■ Cache bypass instructions, such as ldwio and stwio.
February 2014 Altera Corporation
for more information.
Nios II Core Implementation Details
3–4, and "TLB Organization" on page
for more information.
chapter of the Nios II
"Address Space and
3–6.
Nios II Processor Reference Handbook
3–55
"Exception