L4 Slaves - Altera Cyclone V Device Handbook

4-6

L4 Slaves

L4 Slaves
Each of the L4 slaves is an APB slave connected to one of the following five L4 buses:
• L4 slave peripheral (SP) bus APB for peripherals that do not require fast access
• SDRAM controller subsystem CSR access
• SP timer 0 CSR access
• SP timer 1 CSR access
• I2C0 CSR access
• I2C1 CSR access
• I2C2 (associated with EMAC0) CSR access
• I2C3 (associated with EMAC1) CSR access
• UART0 CSR access
• UART1 CSR access
• CAN0 CSR access
• CAN1 CSR access
• L4 master peripheral (MP) bus APB that provides access to primarily the L3 master peripherals.
• ACP ID mapper CSR access
• FPGA manager CSR access
• DAP CSR access
• Quad SPI flash CSR access
• SD/MMC CSR access
• EMAC0 CSR access
• EMAC1 CSR access
• GPIO0 CSR access
• GPIO1 CSR access
• GPIO2 CSR access
• L4 oscillator 1 (OSC1) bus APB dedicated to peripherals that operate on the external oscillator 1 domain.
• OSC1 timer 0 CSR access
• OSC1 timer 1 CSR access
• Watchdog 0 CSR access
• Watchdog 1 CSR access
• Clock manager CSR access
• Reset manager CSR access
• System manager CSR access
• L4 main bus APB dedicated to the DMA and SPI slaves
• DMA_s Access to the DMA controllers secure registers
• DMA_ns Nonsecure access to the DMA controller nonsecure registers
• SPI slave 0 CSR access
• SPI slave 1 CSR access
Altera Corporation
cv_54004
2013.12.30
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