Memory And I/O Organization - Altera Nios II User Manual

Chapter 2: Processor Architecture

Memory and I/O Organization

Internal Interrupt Controller
The Nios II architecture supports 32 internal hardware interrupts. The processor core
has 32 level-sensitive interrupt request (IRQ) inputs, irq0 through irq31, providing a
unique input for each interrupt source. IRQ priority is determined by software. The
architecture supports nested interrupts.
Your software can enable and disable any interrupt source individually through the
ienable control register, which contains an interrupt-enable bit for each of the IRQ
inputs. Software can enable and disable interrupts globally using the PIE bit of the
status control register. A hardware interrupt is generated if and only if all of the
following conditions are true:
The PIE bit of the status register is 1
■
■ An interrupt-request input, irq<n>, is asserted
■ The corresponding bit n of the ienable register is 1
The interrupt vector custom instruction is less efficient than using the EIC interface
with the Altera vectored interrupt controller component, and thus is deprecated in
Qsys. Altera recommends using the EIC interface.
Memory and I/O Organization
This section explains hardware implementation details of the Nios II memory and
I/O organization. The discussion covers both general concepts true of all Nios II
processor systems, as well as features that might change from system to system.
The flexible nature of the Nios II memory and I/O organization are the most notable
difference between Nios II processor systems and traditional microcontrollers.
Because Nios II processor systems are configurable, the memories and peripherals
vary from system to system. As a result, the memory and I/O organization varies
from system to system.
A Nios II core uses one or more of the following to provide memory and I/O access:
Instruction master port—An Avalon
■
that connects to instruction memory via system interconnect fabric
■ Instruction cache—Fast cache memory internal to the Nios II core
■ Data master port—An Avalon-MM master port that connects to data memory and
peripherals via system interconnect fabric
Data cache—Fast cache memory internal to the Nios II core
■
Tightly-coupled instruction or data memory port—Interface to fast on-chip memory
■
outside the Nios II core
The Nios II architecture handles the hardware details for the programmer, so
programmers can develop Nios II applications without specific knowledge of the
hardware implementation.
February 2014 Altera Corporation
®
Memory-Mapped (Avalon-MM) master port
Nios II Processor Reference Handbook
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