On-Chip Memory; Endian Support - Altera Cyclone V Device Handbook

cv_54001
2013.12.30
Related Information
SPI Controller
GPIO Interfaces
The three GPIO interfaces are based on Synopsys DesignWare APB General Purpose Programming I/O
peripheral and offer the following features:
• Supports digital de-bounce
• Configurable interrupt mode
• Supports up to 71 I/O pins and 14 input-only pins, based on device variant
Related Information
General-Purpose I/O Interface

On-Chip Memory

On-Chip RAM
The on-chip RAM offers the following features:
• 64 KB size
• 64-bit slave interface
• High performance for all burst lengths
Related Information
On-Chip Memory
Boot ROM
The boot ROM offers the following features:
• 64 KB size
• Contains the code required to support HPS boot from cold or warm reset
• Used exclusively for booting the HPS
Related Information
On-Chip Memory

Endian Support

The HPS is natively a little-endian system. All HPS slaves are little-endian.
The processors masters are software configurable to interpret data as little-endian or big-endian, byte-
invariant (BE8). All other masters, including the USB interface, are little-endian.
The FPGA-to-HPS, HPS-to-FPGA, FPGA-to-SDRAM, and lightweight HPS-to-FPGA interfaces are little-
endian.
If a processor is set to BE8 mode, software must convert endianness for accesses to peripherals and DMA
linked lists in memory.
Introduction to Cyclone V Hard Processor System (HPS)
Send Feedback
on page 19-1
on page 22-1
on page 9-1
on page 9-1
1-11
GPIO Interfaces
Altera Corporation