Configuration, Status, And Setup Elements - Altera HSMC Reference Manual

2–2
Figure 2–2
Figure 2–2. Data Conversion HSMC—Back View
Table 2–1
Table 2–1. Data Conversion HSMC Feature Overview (Part 1 of 2)
Board Reference

Configuration, Status, and Setup Elements

J3 (Channel A)
J7 (Channel B)
J2 (Channel A)
J6 (Channel B)
J15 (Channel A)
J17 (Channel B)
J11
J10
J13
J23
Clock
J26 (External Clock In-p)
J30 (External Clock In-n)
Data Conversion HSMC Reference Manual
shows the back view of the Data Conversion HSMC.
lists the components and their corresponding board references.
Name
A/D converter clock select
jumper
Power down select jumper
D/A converter clock select
jumper
Mode select jumper
Gain setting select jumper
Sleep select jumper
External clock output select
jumper
External clock input SMA
connectors
Chapter 2: Board Components and Interfaces
HSMC Connector (J1)
Description
Controls which of the three input clock signals
(FPGA clock A, B, or the external SMA clock) is routed
to the A/D converter.
Controls whether the A/D converter operates in
power down or power up state.
Controls which of the three input clock signals
(FPGA clock A, B, or the external SMA clock) is routed
to the D/A converter.
Controls whether the D/A converter operates in dual
bus mode or interleaved mode.
Controls whether the D/A converter channel's gain is
set through one or two resistors.
Controls whether the D/A converter operates in
power down or power up state.
Selects which of the four input clocks (FPGA clock A, B
or A/D converter Data Clock Output) is routed to the
SMA clock out (J28).
SMA connectors for a differential clock input.
Board Overview
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© November 2008 Altera Corporation