Fpga Configuration - Altera Cyclone V Device Handbook

13-4

FPGA Configuration

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Related Information
FPGA Manager Address Map and Register Definitions
FPGA Configuration
You can configure the FPGA using an external device or through the HPS. This section describes configuring
the FPGA through the HPS.
For information about configuring the FPGA using an external device, refer to the Configuration, Design
Security, and Remote System Upgrades chapter in the Cyclone V Device Handbook, Volume 1.
The FPGA CB uses the FPGA mode select (MSEL) pins to determine which configuration scheme to use.
The MSEL pins must be tied to the appropriate values for the configuration scheme. The table below lists
supported MSEL values when the FPGA is configured by the HPS.
HPS software sets the clock-to-data ratio field (cdratio) and configuration data width bit (cfgwdth) in
the control register (ctrl) to match the MSEL pins. The cdratio field and cfgwdth bit must be set
before the start of configuration.
The FPGA manager connects to the configuration logic in the FPGA portion of the device using a mode
similar to how external logic (for example, MAX II or an intelligent host) configures the FPGA in fast passive
parallel (FPP) mode. FPGA configuration through the HPS supports all the capabilities of FPP mode,
including the following items:
• FPGA configuration
• Partial FPGA reconfiguration
• FPGA I/O configuration, followed by PCI Express
• External single event upset (SEU) scrubbing
• Decompression
• Advanced Encryption Standard (AES) encryption
• FPGA DCLK clock used for initialization phase clock
Note: The FPGA manager supports a data width of 32 or 16 bits. When configuring the FPGA fabric from
the HPS, Altera recommends that you always set the data width to 32 bits. For partial reconfiguration,
the 16-bit data width is the only option.
The following table lists the supported configuration schemes and their respective MSEL and control register
settings when the HPS configures the FPGA.
Altera Corporation
on page 13-8
® ®
(PCIe ) configuration of the remainder of FPGA
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2013.12.30
FPGA Manager
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