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Chapter 2: Board Components
Configuration, Status, and Setup Elements
Although there is only one clock generator PLL on the SDI HSMC, the board supports
two asynchronous clock systems when the host board supports two reference clock
input signals. You can use either a separate reference clock or an external reference as
input to the host board.
Table 2–3
frequency for each supported audio sample rate.
Table 2–3. AES3 Supported Bit Rates
Audio Sample Rate (kHz)
Configuration, Status, and Setup Elements
This section describes board configuration, status, and setup.
Configuration
The standard jumper configuration has J4 (CD_MUTE2) and J6 (CD_MUTE1) installed.
Jumpers J5 (EQ_BYPASS2) and J7 (EQ_BYPASS1) can be driven from the host board.
These signals bypass the SDI cable equalizer when logic 1 is driven.
Status Elements
The development board includes status LEDs. This section describes the status
elements.
Table 2–4
© July 2009 Altera Corporation
describes the features of the oversampling rate and associated clock
Bit Rate Clock (MHz)
(32 x 2 x 2)
24.0
32
44.1
48
88.2
11.2896
96
12.2880
176.4
22.5792
192
24.5760
24.0
32
44.1
48
88.2
11.2896
96
12.2880
176.4
22.5792
192
24.5760
lists the LED board references and functional descriptions.
Oversampling Rate
3.0720
32
4.0960
24
5.6448
16
6.1440
16
3.0720
40
4.0960
30
5.6448
20
6.1440
20
10
10
VCXO Frequency
98.304
98.304
90.3168
98.304
8
90.3168
8
98.304
4
90.3168
4
98.304
122.8800
122.8800
112.8960
122.8800
112.8960
122.8800
5
112.8960
5
122.8800
SDI HSMC Reference Manual
2–5
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