Reset And Debug Signals; Exception And Interrupt Controllers - Altera Nios II User Manual

Chapter 2: Processor Architecture

Reset and Debug Signals

Reset and Debug Signals
The table below describes the reset and debug signals that the Nios II processor core
supports.
Table 2–4. Nios II Processor Debug and Reset Signals
Signal Name Type
Reset
reset
Reset
cpu_resetrequest
Debug
debugreq
Reset
reset_req
f
For more information on adding reset signals to the Nios II processor, refer to
"Advanced Features Tab" in the
Processor Reference Handbook.
For more information on the break vector and adding debug signals to the Nios II
processor, refer to "JTAG Debug Module Tab" in the
chapter of the Nios II Processor Reference Handbook.

Exception and Interrupt Controllers

The Nios II processor includes hardware for handling exceptions, including hardware
interrupts. It also includes an optional external interrupt controller (EIC) interface.
The EIC interface enables you to speed up interrupt handling in a complex system by
adding a custom interrupt controller.
February 2014 Altera Corporation
Purpose
This is a global hardware reset signal that forces the processor core to reset
immediately.
This is an optional, local reset signal that causes the processor to reset without
affecting other components in the Nios II system. The processor finishes executing any
instructions in the pipeline, and then enters the reset state. This process can take
several clock cycles, so be sure to continue asserting the cpu_resetrequest signal
until the processor core asserts a
The processor core asserts a
complete and then periodically if cpu_resetrequest remains asserted. The processor
remains in the reset state for as long as cpu_resetrequest is asserted. While the
processor is in the reset state, it periodically reads from the reset address. It discards
the result of the read, and remains in the reset state.
The processor does not respond to cpu_resetrequest when the processor is under
the control of the JTAG debug module, that is, when the processor is paused. The
processor responds to the cpu_resetrequest signal if the signal is asserted when
the JTAG debug module relinquishes control, both momentarily during each single step
as well as when you resume execution.
This is an optional signal that temporarily suspends the processor for debugging
purposes. When you assert the signal, the processor pauses in the same manner as
when a breakpoint is encountered, transfers execution to the routine located at the
break address, and asserts a debugack signal. Asserting the debugreq signal when
the processor is already paused has no effect.
This optional signal prevents the memory corruption by performing a reset handshake
before the processor resets.
Instantiating the Nios II Processor
cpu_resettaken signal.
cpu_resettaken signal for 1 cycle when the reset is
Instantiating the Nios II Processor
Nios II Processor Reference Handbook
2–9
chapter of the Nios II