Reset Pins - Altera Cyclone V Device Handbook

3-12
Warm Reset Assertion Sequence
Warm Reset Assertion Sequence
The following list describes the assertion steps for warm reset shown in the Warm Reset Timing Diagram:
1. Optionally, handshake with the embedded trace router (ETR) and wait for acknowledge.
2. Optionally, handshake with the FPGA fabric and wait for acknowledge.
3. Optionally, handshake with the SDRAM controller, scan manager, and FPGA manager, and wait for
acknowledges.
4. Assert module resets (except the MPU watchdog timer resets when the MPU watchdog timers are the
only request sources).
5. Wait for 8 cycles and send a safe mode request to the clock manager.
6. Wait for the greater of the nRST pin count + 256 stretch count, or the warm reset counter, or the clock
manager safe mode acknowledge, then deassert all handshakes except warm reset ETR handshake (which
is deasserted by software).
7. Proceed to the "Cold and Warm Reset Deassertion Sequence" section using the following link.
Related Information
Cold and Warm Reset Deassertion Sequence
Cold and Warm Reset Deassertion Sequence
The following list describes the deassertion steps for both cold and warm reset shown in the Cold Reset
Timing Diagram and Warm Reset Timing Diagram:
1. Deassert L3 reset.
2. Wait for 100 cycles. Deassert resets for miscellaneous-type and debug (cold only) modules.
3. Wait for 200 cycles. Assert mpu_clkoff for CPU0 and CPU1.
4. Wait for 32 cycles. Deassert resets for MPU modules.
5. Wait for 32 cycles. Deassert mpu_clkoff for CPU0 and CPU1.
6. Peripherals remain held in reset until software brings them out of reset.

Reset Pins

Figure 3-5: Reset Pins
Altera Corporation
HPS
nTRST
TMS
TCK
nPOR
nRST
on page 3-12
SoC Device
ARM DAP
Reset Manager
rst_pin_rst_n
cv_54003
2013.12.30
Reset Manager
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