External Memory Interfacing; Pad Placement And Dc Guidelines; Pad Placement; Dc Guidelines - Altera Cyclone IV Device Handbook

Chapter 6: I/O Features in Cyclone IV Devices

Pad Placement and DC Guidelines

External Memory Interfacing

Cyclone IV devices support I/O standards required to interface with a broad range of
external memory interfaces, such as DDR SDRAM, DDR2 SDRAM, and QDR II
SRAM.
f
For more information about Cyclone IV devices external memory interface support,
refer to the
Pad Placement and DC Guidelines
You can use the Quartus II software to validate your pad and pin placement.

Pad Placement

Altera recommends that you create a Quartus II design, enter your device I/O
assignments and compile your design to validate your pin placement. The Quartus II
software checks your pin connections with respect to the I/O assignment and
placement rules to ensure proper device operation. These rules depend on device
density, package, I/O assignments, voltage assignments and other factors that are not
fully described in this chapter.
f
For more information about how the Quartus II software checks I/O restrictions, refer
to the

DC Guidelines

For the Quartus II software to automatically check for illegally placed pads according
to the DC guidelines, set the DC current sink or source value to Electromigration
Current assignment on each of the output pins that are connected to the external
resistive load.
The programmable current strength setting has an impact on the amount of DC
current that an output pin can source or sink. Determine if the current strength setting
is sufficient for the external resistive load condition on the output pin.

Clock Pins Functionality

Cyclone IV clock pins have multiple purposes, as per listed:
■ CLK pins—Input support for single-ended and voltage-referenced standards. For
I/O standard support, refer to
■ DIFFCLK pins—Input support for differential standards. For I/O standard support,
refer to
can be used depending on the interface requirements and external termination is
required. For more information, refer to
page
■ REFCLK pins—Input support for high speed differential reference clocks used by
the transceivers in Cyclone IV GX devices. For I/O support, coupling, and
termination requirements, refer to
March 2016 Altera Corporation
External Memory Interfaces in Cyclone IV Devices
I/O Management chapter in volume 2 of the Quartus II Handbook.
Table 6–3 on page 6–11. When used as DIFFCLK pins, DC or AC coupling
6–28.
Table 6–3 on page 6–11.
"High-Speed I/O Standards Support" on
Table 6–10 on page 6–29.
6–23
chapter.
Cyclone IV Device Handbook,
Volume 1