Reset Manager Block Diagram And System Integration; Hps External Reset Sources - Altera Cyclone V Device Handbook

cv_54003
2013.12.30

Reset Manager Block Diagram and System Integration

Figure 3-1: Reset Manager Block Diagram
The following figure shows a block diagram of the reset manager in the SoC device. For clarity, reset-related
handshaking signals to other HPS modules and to the clock manager module are omitted.
nPOR
nRST

HPS External Reset Sources

The following table lists the reset sources external to the HPS. All signals are synchronous to the osc1_clk
clock. The reset signals from the HPS to the FPGA fabric must be synchronized to your user logic clock
domain.
Table 3-2: HPS External Reset Sources
f2h_cold_rst_req_n
Reset Manager
Send Feedback
FPGA Portion
Control
Block
load_csr usermode
HPS
Scan Manager Reset Request
Scan Manager
Watchdog Reset Request[1:0]
MPU
Debug Reset Request
DAP
POR Voltage Reset Request
POR Voltage
Detector
System Watchdog Reset Request[1:0]
Watchdog (2)
Source
Reset Manager Block Diagram and System Integration
FPGA Fabric
f2h_dbg_rst_req_n
f2h_cold_rst_req_n
f2h_warm_rst_req_n
Reset
Controller
(swcoldrstreq and
swwarmrstreq bits of ctrl)
L4 Peripheral Bus (osc1_clk)
Cold reset request from FPGA fabric (active low)
h2f_rst_n
h2f_cold_rst_n
Reset Manager
fpga_config_complete
Signal
Assertion /
De-Assertion
(mpumodrst,
permodrst,
per2modrst,
brgmodrst,
and
miscmodrst)
CSRs
Slave Interface
Description
3-3
HPS
Modules
Module
Reset
Signals
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