Cortex-A9 Mpu Subsystem Block Diagram And System Integration; Cortex-A9 Mpu Subsystem With L3 Interconnect - Altera Cyclone V Device Handbook

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Cortex-A9 MPU Subsystem Block Diagram and System Integration

Cortex-A9 MPU Subsystem Block Diagram and System Integration

Cortex-A9 MPU Subsystem with L3 Interconnect

This figure shows a dual-core MPU subsystem in the context of the HPS, with the L2 cache. The L2 cache
can access either the level 3 (L3) interconnect fabric or the SDRAM.
Altera Corporation
L3 Interconnect MPU Subsystem
(NIC-301)
ACP ID
Mapper
M0
ARM Cortex-A9 MPCore
Interrupts
CPU0 CPU1
Debug Infrastructure
ACP SCU
L2 Cache
M1
SDRAM
Controller
Subsystem
Cortex-A9 Microprocessor Unit Subsystem
cv_54006
2013.12.30
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