Security; Arbitration; Cyclic Dependency Avoidance Schemes - Altera Cyclone V Device Handbook

cv_54004
2013.12.30
At reset time, the system manager drives the cache and buffering signals for these masters low. In other
words, the masters listed do not support cacheable or bufferable accesses until you enable them after reset.
There is no synchronization between the system manager and the interconnect, so avoid changing these
settings when any of the masters are active.
Related Information
System Manager
For more information about enabling or disabling this feature, refer to the System Manager chapter.

Security

Slave Security
The interconnect enforces security through the slave settings. The slave settings are controlled by the address
region control registers accessible through the GPV registers. Each L3 and L4 slave has its own security check
and programmable security settings. After reset, every slave of the interconnect is set to a secure state (referred
to as boot secure). The only accesses allowed to secure slaves are by secure masters.
The GPV can only be accessed by secure masters. The security state of the interconnect is not accessible
through the GPV as the security registers are write-only. Any nonsecure accesses to the GPV receive a
DECERR response, and no register access is provided. Updates to the security settings through the GPV do
not take effect until all transactions to the affected slave have completed.
Master Security
Masters of the interconnect are either secure, nonsecure, or the security is set on a per transaction basis. The
DAP is capable of performing only secure accesses. The L2 cache master 0, FPGA-to-HPS-bridge, and DMA
perform secure and nonsecure accesses on a per transaction basis. All other interconnect masters perform
nonsecure accesses.
Accesses to secure slaves by unsecure masters result in a response of DECERR and the transaction does not
reach the slave.
Related Information
Interconnect Master Properties

Arbitration

At the entry point to the interconnect, all transactions are allocated a local quality of service (QoS) value
that you can programmatically configure. The arbitration of the transaction throughout the infrastructure
uses this QoS value. The QoS controls for each master connected to the interconnect are separated into read
and write QoS priority values.
At any arbitration node, a fixed priority exists for transactions with different QoS values. The highest QoS
value has the highest priority. If there are coincident transactions at an arbitration node with the same QoS
value that require arbitration, then the interconnect uses a least recently used (LRU) algorithm.

Cyclic Dependency Avoidance Schemes

The AXI protocol permits re-ordering of transactions. As a result, when routing concurrent multiple
transactions from a single point of divergence to multiple slaves, the interconnect might need to enforce
rules to prevent deadlock.
Interconnect
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