Functional Description Of The Interconnect; Master To Slave Connectivity Matrix - Altera Cyclone V Device Handbook

cv_54004
2013.12.30
• L4 SPI master (SPIM) bus APB dedicated to the SPI masters and scan manager.
• SPI master 0 CSR access
• SPI master 1 CSR access
• Scan manager CSR access

Functional Description of the Interconnect

Master to Slave Connectivity Matrix

The interconnect is a partially-connected crossbar. The following table shows the connectivity matrix of all
the master and slave interfaces of the interconnect.
Table 4-2: Interconnect Connectivity Matrix
L2 Cache Master 0
Interconnect
Send Feedback
Masters
Functional Description of the Interconnect
Connected Slaves
• L4 SP Bus Slaves
• L4 MP Bus Slaves
• L4 OSC1 Bus Slaves
• L4 MAIN Bus Slaves
• L4 SPIM Bus Slaves
• Lightweight HPS-to-FPGA Bridge
• USB OTG 0/1 CSR
• NAND CSR
• NAND Command and Data
• Quad SPI Flash Data
• FPGA Manager
• HPS-to-FPGA Bridge
• STM
• Boot ROM
• On-Chip RAM
4-7
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