Clock Manager Block Diagram And System Integration - Altera Cyclone V Device Handbook

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Clock Manager Block Diagram and System Integration

• Allows software to program clock characteristics, such as the following items discussed later in this
chapter:
• Input clock source for SDRAM and peripheral PLLs
• Multiplier range, divider range, and six post-scale counters for each PLL
• Output phases for SDRAM PLL outputs
• VCO enable for each PLL
• Bypass modes for each PLL
• Gate off individual clocks in all PLL clock groups
• Clear loss of lock status for each PLL
• Safe mode for hardware-managed clocks
• General-purpose I/O (GPIO) debounce clock divide
• Allows software to observe the status of all writable registers
• Supports interrupting the MPU subsystem on PLL-lock and loss-of-lock
• Supports clock gating at the signal level
The clock manager is not responsible for the following functional behaviors:
• Selection or management of the clocks for the FPGA-to-HPS, HPS-to-FPGA, and FPGA-to-HPS SDRAM
interfaces. The FPGA logic designer is responsible for selecting and managing these clocks.
• Software must not program the clock manager with illegal values. If it does, the behavior of the clock
manager is undefined and could stop the operation of the HPS. The only guaranteed means for recovery
from an illegal clock setting is a cold reset.
Related Information
Hardware-Managed and Software-Managed Clocks
When re-programming clock settings, there are no automatic glitch-free clock transitions. Software must
follow a specific sequence to ensure glitch-free clock transitions. Refer to Hardware-Managed and
Software-Managed Clocks section of this chapter.
Clock Manager Block Diagram and System Integration
The following figure shows the major components of the clock manager and its integration in the HPS.
Altera Corporation
on page 2-5
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2013.12.30
Clock Manager
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