Mpu Subsystem; Interconnect; Memory Controllers - Altera Cyclone V Device Handbook

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MPU Subsystem

MPU Subsystem
The MPU subsystem provides the following functionality:
• ARM Cortex-A9 MPCore
• One or two ARM Cortex-A9 processors in a cluster
™
• NEON
• Snoop Control Unit (SCU) to ensure coherency within the cluster
• Accelerator coherency port (ACP) that accepts coherency memory access requests
• Interrupt controller
• One general-purpose timer and one watchdog timer per processor
• Debug and trace features
• 32 KB instruction and 32 KB data level 1 (L1) caches per processor
• Memory management unit (MMU) per processor
• ARM L2-310 level 2 (L2) cache
• Shared 512 KB L2 cache
• ACP ID mapper
• Maps the 12-bit ID from the level 3 (L3) interconnect to the 3-bit ID supported by the ACP
As shown in the HPS Block Diagram, the L2 cache has one 64-bit master port connected to the L3
interconnect, one 64 -bit master port connected directly to the SDRAM L3 Interconnect, and three ports
that connect the FPGA to the SDRAM L3 Interconnect. A programmable address filter in the L2 cache
controls which portions of the 32-bit physical address space use which master.
Related Information
Cortex-A9 Microprocessor Unit Subsystem

Interconnect

The interconnect consists of the L3 interconnect and level 4 (L4) buses. The L3 interconnect is one ARM
NIC-301 module composed of the following switches:
The L4 buses are each connected to a master in the L3 slave peripheral switch. Each L4 bus is 32 bits wide
and is connected to multiple slaves. Each L4 bus operates on a separate clock source.
Related Information
Interconnect on page 4-1

Memory Controllers

SDRAM Controller Subsystem
The SDRAM controller subsystem is mastered by HPS masters and FPGA fabric masters.
Altera Corporation
SIMD coprocessor and VFPv3 per processor
on page 6-1
Introduction to Cyclone V Hard Processor System (HPS)
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2013.12.30
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