cv_54009
2013.12.30
Boot ROM
This section describes hardware aspects of the HPS boot ROM.
Features of the Boot ROM
The boot ROM offers the following features:
• 32-bit interface
• 64 KB size
• Single-ported ROM
• Read acceptance of two
• Sustained ideal throughput (operating frequency times the data width) during read after read.
Related Information
Clock Manager
For more information about the operating frequency and maximum throughput, refer to the Clock Manager
chapter.
Boot ROM Block Diagram and System Integration
Transfers between memory and the NIC-301 L3 interconnect happen through a 32-bit data interface, gated
by the l3_main_clk interconnect clock.
The entire RAM is either secure or nonsecure. Security is enforced by the NIC-301 L3 interconnect.
Figure 9-2: Boot ROM Block Diagram
Related Information
Interconnect
For more information about security, refer to the Interconnect chapter.
Functional Description of the Boot ROM
The boot ROM is used only for booting the system. On a cold or warm reset of the microprocessor unit
(MPU) subsystem, MPU0 executes the pre-bootloader code stored in the boot ROM.
The boot ROM uses an 32-bit slave interface. The slave interface supports transfers between memory and
the NIC-301 L3 interconnect. All writes return an error response.
On-Chip Memory
Send Feedback
on page 2-1
NIC-301
L3 Interconnect
M
on page 4-1
Boot ROM
Data Interface
S
9-3
Boot ROM
Altera Corporation