Rom Mode; Fifo Buffer Mode - Altera Cyclone IV Device Handbook

Chapter 3: Memory Blocks in Cyclone IV Devices
Memory Modes
Figure 3–12
Figure 3–12. Cyclone IV Devices Shift Register Mode Configuration
w × m × n Shift Register
m-Bit Shift Register
W
m-Bit Shift Register
W
m-Bit Shift Register
W
m-Bit Shift Register
W

ROM Mode

Cyclone IV devices M9K memory blocks support ROM mode. A .mif initializes the
ROM contents of these blocks. The address lines of the ROM are registered. The
outputs can be registered or unregistered. The ROM read operation is identical to the
read operation in the single-port RAM configuration.

FIFO Buffer Mode

Cyclone IV devices M9K memory blocks support single-clock or dual-clock FIFO
buffers. Dual clock FIFO buffers are useful when transferring data from one clock
domain to another clock domain. Cyclone IV devices M9K memory blocks do not
support simultaneous read and write from an empty FIFO buffer.
f
For more information about FIFO buffers, refer to the
Megafunction User
November 2011 Altera Corporation
shows the Cyclone IV devices M9K memory block in shift register mode.
Guide.
W
W
n Number of Taps
W
W
Single- and Dual-Clock FIFO
Cyclone IV Device Handbook,
3–13
Volume 1