Hps Debug Apb Interface; Coresight Debug And Trace Programming Model; Rom Table - Altera Cyclone V Device Handbook

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HPS Debug APB Interface

Related Information
Info center
For more information, refer to the CoreSight PTM-A9 Technical Reference Manual.
HPS Debug APB Interface
The HPS can extend the CoreSight debug control bus into the FPGA fabric. The debug interface is an APB-
compatible interface with built-in clock crossing.
Related Information
HPS Component Interfaces

CoreSight Debug and Trace Programming Model

This section describes programming model details specific to Altera's implementation of the ARM CoreSight
technology.
The debug components can be configured to cause triggers when certain events occur. For example, soft
logic in the FPGA fabric can signal an event which triggers an STM message injection into the trace stream.
CoreSight components are configured through memory-mapped registers, located at offsets relative to the
CoreSight component base address. CoreSight component base addresses are accessible through a ROM
table.
Related Information
Info center
Programming interface details of each CoreSight component.

ROM Table

Table 7-1: DAP ROM Table
The following table contains entries found in the ROM table portion of the DAP.
ROM Entry
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
Altera Corporation
on page 28-1
Offset[30:12]
0x00001
0x00002
0x00003
0x00004
0x00005
0x00006
0x00007
0x00100
0x00080
cv_54007
2013.12.30
Description
ETF
CTI
TPIU
Trace Funnel
STM
ETR
FPGA-CTI
A9ROM
FPGAROM
CoreSight Debug and Trace
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