Hard Ip For Pci Express (Cyclone Iv Gx Devices Only) - Altera Cyclone IV Device Handbook

Chapter 1: Cyclone IV FPGA Device Family Overview
Cyclone IV Device Family Architecture
Figure 1–1
Figure 1–1. Transceiver Channel for the Cyclone IV GX Device
FPGA
Fabric
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For more information, refer to the

Hard IP for PCI Express (Cyclone IV GX Devices Only)

Cyclone IV GX devices incorporate a single hard IP block for ×1, ×2, or ×4 PCIe (PIPE)
in each device. This hard IP block is a complete PCIe (PIPE) protocol solution that
implements the PHY-MAC layer, Data Link Layer, and Transaction Layer
functionality. The hard IP for the PCIe (PIPE) block supports root-port and end-point
configurations. This pre-verified hard IP block reduces risk, design time, timing
closure, and verification. You can configure the block with the Quartus II software's
PCI Express Compiler, which guides you through the process step by step.
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For more information, refer to the
March 2016 Altera Corporation
shows the structure of the Cyclone IV GX transceiver.
TX Phase
Compensation Byte Serializer
FIFO
Cyclone IV Transceivers Architecture
PCI Express Compiler User
Transmitter Channel PCS
8B10B Encoder
Receiver Channel PCS
1–11
Transceiver Channel
PMA
Receiver Channel
PMA
chapter.
Guide.
Cyclone IV Device Handbook,
Volume 1