Fpga Manager Block Diagram And System Integration - Altera Cyclone V Device Handbook

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FPGA Manager Block Diagram and System Integration

Figure 13-1: FPGA Manager Block Diagram

Interconnect

The register slave interface connects to the level 4 (L4) master peripheral bus for control and status register

(CSR) access. The configuration slave interface connects to the level 3 (L3) interconnect for the microprocessor

unit (MPU) subsystem or other masters to write the FPGA configuration image to the FPGA control block

(CB) when configuring the FPGA portion of the SoC device.

The general-purpose I/O and boot handshaking input interfaces connect to the FPGA fabric. The FPGA

manager also connects to the FPGA CB signals to monitor and control the FPGA portion of the device.

The FPGA manager consists of the following blocks:

• Configuration slave interface accepts and transfers the configuration image to the data interface.

• Register slave interface accesses the CSRs in the FPGA manager.

• Data accepts the FPGA configuration image from the configuration slave interface and sends it to the

• Control controls the FPGA CB.

• Monitor monitors the configuration signals in the FPGA CB and sends interrupts to the MPU subsystem.

• Fabric I/O reads and writes signals from or to the FPGA fabric.

Altera Corporation

FPGA Manager

Configuration

FPGA Portion

Control Block

CONFIG_IO Mode

CVP_CONF_DONE

h2f_gp[31:0]

f2h_gp[31:0]

f2h_boot_from_fpga_on_failure

f2h_boot_from_fpga_ready

FPGA Manager

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