Module Reset Signals - Altera Cyclone V Device Handbook

cv_54003
2013.12.30
Figure 3-2: Reset Controller Signals
The reset controller supports the following cold reset requests:
• Power-on reset (POR) voltage monitor
• Cold reset request pin (nPOR)
• FPGA fabric
• FPGA CB and scan manager
• Software cold reset request bit (swcoldrstreq) of the control register (ctrl)
The reset controller supports the following warm reset requests:
• Warm reset request pin (nRST)
• FPGA fabric
• Software warm reset request bit (swwarmrstreq) of the ctrl register
• MPU watchdog reset requests for CPU0 and CPU1
• System watchdog timer 0 and 1 reset requests
The reset controller supports the following debug reset requests:
• CDBGRSTREQ from DAP
• FPGA fabric

Module Reset Signals

The following table lists the module reset signals. The module reset signals are organized in groups for the
MPU, peripherals, bridges, the level 3 (L3) interconnect, and miscellaneous.
Reset Manager
Send Feedback
POR Voltage Monitor
nPOR Pin
FPGA Fabric (f2h_cold_rst_req_n)
FPGA CB & Scan Manager
nRST Pin
FPGA Fabric (f2h_warm_rst_req_n)
MPU Watchdog Reset [1:0]
System Watchdog Reset [1:0]
CDBGRSTREQ (DAP)
FPGA Fabric (f2h_dbg_rst_req_n)
ETR
SDRAM Self-Refresh
FPGA Manager
SCAN Manager
FPGA Fabric
Reset Controller
Cold
Module Resets
Reset
Requests
Debug Domain
Reset
TAP Domain
Warm
Reset
Reset
Requests
MPU Clock
Gating
Debug
Reset
Requests
Reset
Reset
Handshaking
Handshaking
Outputs
Inputs
Reset Manager osc1_clk
APB Slave Interface
Module Reset Signals
Many Signals (refer to Table 3-3)
dbg_rst_n
JTAG TAP (DAP)
CPUCLKOFF[1:0]
CDBGRSTACK (DAP)
ETR
SDRAM Self-Refresh
FPGA Manager
SCAN Manager
FPGA
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