Reset Manager - Altera Cyclone V Device Handbook

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The reset manager generates module reset signals based on reset requests from the various sources in the

HPS and FPGA fabric, and software writing to the module-reset control registers. The reset manager ensures

that a reset request from the FPGA fabric can occur only after the FPGA portion of the system-on-a-chip

(SoC) device is configured.

The HPS contains three reset domains. Each reset domain can be reset independently. Each register in the

HPS that can be reset belongs to one particular reset domain.

Table 3-1: HPS Reset Domains

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JTAG test access port (TAP) controller, which is used by the debug access

All debug logic including most of the DAP, CoreSight

connected to the debug peripheral bus, trace, the microprocessor unit

(MPU) subsystem, and the FPGA fabric.

All HPS logic except what is in the TAP and debug reset domains.

Includes nondebug logic in the FPGA fabric connected to the HPS reset

Reset Manager

Domain Logic

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